A. Field of the Invention
The present invention relates to electronic design, and more particularly to analysis of signal timing requirements in complex electronic systems.
B. Description of the Prior Art
Digital processing systems typically consist of a combinational logic network and bistable latch elements. The combinational logic network contains a large number of logic components that perform decision-making functions, while the latches serve as memory elements to temporarily store input, intermediate and output data, as well as control information. A clocking system mediates communication among the system components and state changes in the individual elements; usually, the state of the system changes at the occurrence of each clock pulse.
Components and groups of components have timing requirements that derive from specific operational features. Some requirements arise from hardware limitations; for example, a component may require establishment of a stable input signal for a certain minimum time interval before a stable output signal from that component can be achieved. Other requirements arise from system features such as bus characteristics, interface protocols or cycle times. Given the large number of interrelated timing requirements likely to be encountered in the design of even modest digital systems, methods of identifying and resolving timing conflicts are critical.
Two such methods are described in copending application Ser No. 162,624 U.S. Pat. No. 4,965,758 and Ser. No. 205,811 U.S. Pat. No. 5,218,783 (both of which are commonly owned with the present application and are hereby incorporated by reference) The '624 application describes identification of an optimized, reduced set of consistent timing requirements that deviates minimally from the set originally proposed by the user. This is accomplished by representing related timing constraints as a tree, with the the events specified in the constraint serving as vertices and the associations among such events serving as arcs.
The '811 application describes adjustment of dependences to accommodate conflicting timing requirements. As in the '624 application, timing constraints are represented as a set of arcs and vertices. The invention of the '811 application is directed toward identifying and resolving relationships among sets of constraints that graphically appear as cycles. If the constraints in a cycle impose inconsistent timing requirements, the invention identifies which constraints are most easily modified to render the cycle self-consistent. See also Sherman, Algorithms for Timing Requirement Analysis and Generation, Proc. of 25th ACM/IEEE Design Automation Conf. at 724 (1988).
Unfortunately, engineers rarely encounter system or component timing constraints expressed directly. Instead, they must usually infer constraints among the various signals from individual timing requirements, or "specifications", of each component or system characteristic. For example, the read-write cycle of a static random-access memory (RAM) device typically includes minimum address-line and data-line setup times, a hold time, and a maximum valid data time; these constraints ultimately relate data, address and clock signals to one another, but each concerns only a specific interval.
The difficulty of translating these individual requirements into an overall picture of signal interactions is considerable. Timing requirements suggest, but do not define, pattern characteristics of the signals to which they relate. Yet knowledge of these pattern characteristics may be critical for determining compatibility among requirements that affect the same signals, or for understanding relationships among the requirements. Like pieces of a large puzzle, individual timing requirements must be assembled into a self-consistent aggregate before compatibility issues can even be reached; unlike a puzzle, however, timing requirements must relate to the underlying signals as well as to each other.